The present invention relates to an output circuit of a semiconductor integrated circuit. In particular, the present invention relates to a circuit for controlling the rise time/fall time of an output signal in an output circuit having a CMOS configuration. The present invention is used in USB (Universal Serial Bus) ports of personal computers and peripheral devices having a relatively medium or low speed.
It is important as a technique for preventing occurrence of switching noise to control the inclination of a signal waveform at the time of fall and rise of an output signal of an output circuit of a large scale integrated circuit (LSI), i.e., control the fall time and rise time of the output signal.
FIG. 1 shows the configuration of a typical output circuit section of an LSI used in USB ports of personal computers.
This output circuit section uses two power supplies. This output circuit section includes two-stage inverting amplifier circuits 11 and 12 operating with a first power supply potential VDD, and two CMOS output circuits 13 and 14 operating with the first power supply potential VDD and a second power supply potential VCC.
An input signal IN is supplied to the inverting amplifier circuit 11. An output signal IN1 is outputted from the inverting amplifier circuit 11. The output signal IN1 from the inverting amplifier circuit 11 is supplied to the other inverting amplifier circuit 12. An output signal IN2 is outputted from the inverting amplifier circuit 12.
The output signal IN2 of the inverting amplifier circuit 12 is inputted to a first input terminal INA of a first output circuit 13 and a second input terminal INB of a second output circuit 14. The output signal IN1 of the inverting amplifier circuit 11 is inputted to a second input terminal INB of the first output circuit 13 and a first input terminal INA of the second output circuit 14.
On the basis of two inputted signals IN1 and IN2, the two output circuits 13 and 14 output signals OUT-PLUS and OUT-MNUS having levels which are complementary to each other to an external bus which is not illustrated.
FIG. 2 shows a conventional concrete circuit configuration of the first output circuit 13 among two output circuits 13 and 14 shown in FIG. 1.
This output circuit includes a voltage comparator circuit 21 of CMOS type operating with a first power supply potential VDD (for example, 5 V), an output stage circuit 22 and an output drive control circuit 23 operating with a second power supply potential VCC (for example, 3.3 V), and a feedback capacitor C1 connected between an output terminal BOUTP of the output stage circuit 22 and an output node n1 of the voltage comparator circuit 21 to control the rise time/fall time of an output signal.
The voltage comparator circuit 21 includes a current source I1, P-channel MOS transistors (hereafter referred to as PMOS transistors) MP1 and MP2, and N-channel MOS transistors (hereafter referred to as NMOS transistors) MN1 and MN2. The output stage circuit 22 includes a PMOS transistor MP4 and an NMOS transistor MN5. The output drive control circuit 23 includes a PMOS transistor MP3 and NMOS transistors MN3 and MN4.
The voltage comparator circuit 21 is a circuit of differential input type supplied with the output signals IN1 and IN2 fed from the two-stage inverting amplifier circuits 11 and 12 shown FIG. 1. An output signal fed from an output node n1 of the voltage comparator circuit 21 is inputted to gate of an NMOS transistor MN5 of pull-down side in the output stage circuit 22. The output drive control circuit 23 receives the output signal of the node n1 of the voltage comparator circuit 21, and outputs a signal to be inputted to gate of a PMOS transistor MP4 of pull-up side in the output stage circuit 22.
It should be noted that in the second output circuit 14 of FIG. 1 the connection relations of the complementary input signals IN1 and IN2 inputted to the voltage comparator circuit 21 are opposite to those described above.
Source of the PMOS transistor MP4 of pull-up side is connected to a node of the second power supply voltage VCC, and drain of the PMOS transistor MP4 is connected to the output terminal BOUTP. Furthermore, drain of the NMOS transistor MN5 of pull-down side is connected to the output terminal BOUTP, and drain of the NMOS transistor MN5 is connected to a node of a ground potential DGND.
FIG. 3 shows an example of a simulation result of input-output characteristics of the output circuit section of FIG. 1 using the conventional output circuit shown in FIG. 2.
When the input signal IN is 5 V, the signal IN1 is 0 V and the signal IN2 is 5V.
At this time, in the first output circuit 13, the output signal of the voltage comparator circuit 21 becomes 0 V, the output signal of the output drive control circuit 23 becomes a voltage close to 0 V. The PMOS transistor MP4 of pull-up side turns on, and the NMOS transistor MN5 of pull-down side turns off. Therefore, a signal OUT-PLUS outputted from the output terminal BOUTP becomes "H" (3.3 V).
On the other hand, when the input signal IN is 5 V, the output signal of the voltage comparator circuit 21 becomes 5 V in the second output circuit 14 as described above. The PMOS transistor MP4 of pull-up side turns off, and the NMOS transistor MN5 of pull-down side turns on. An output signal OUT-MNUS outputted from the output circuit becomes "L" (close to 0 V).
When the input signal IN has changed from 5V to 0 V, the signal IN1 changes from 0 V to 5 V and the signal IN2 changes from 5 V to 0 V. In the first output circuit 13, therefore, the signal potential of the output node n1 of the voltage comparator circuit 21 rises from 0 V toward 5 V. At this time, the capacitor element C1 is charged, and consequently the rise rate of the potential of the node n1 becomes slow. As a result of the potential rise of the node n1, the NMOS transistor MN5 of pull-down side turns on and the PMOS transistor MP4 of pull-up side turns off. As a result, the potential of the output terminal BOUTP (the output signal OUT-PLUS) falls from "H" (VCC=3.3 V) toward "L" (close to 0 V).
At this time, as the potential of the output terminal BOUTP falls, the capacitor element C1 is charged. As a result, the node n1 is pulled toward the ground potential GND, and the rise rate of the potential of the node n1 becomes slower. Therefore, the fall rate at the time when the on-resistance of the NMOS transistor MN5 of pull-down side is lowered by the potential rise of the node n1 is further made slow. The fall rate of the potential of the output terminal BOUTP is also lowered.
At this time, the NMOS transistor MN5 of pull-down side has a threshold voltage of approximately 0.7 V. In such a process that the gate input voltage changes from 0 V to 5 V, the NMOS transistor MN5 of pull-down side remains off until the gate input voltage reaches 0.7 V. If the gate input voltage exceeds 0.7 V, the on-current gradually flows and the on-resistance gradually decreases. Therefore, the fall timing of the output signal OUT-PLUS becomes later than the timing of the change of the input signal IN from 5 V to 0 V. In FIG. 3, this delay time is denoted by t1.
On the other hand, when the input signal IN has changed from 5 V to 0 V, the potential of the node n1 of the voltage comparator circuit 21 falls from 5 V toward 0 V as described earlier. As a result, the PMOS transistor MP4 of pull-up side turns on and the NMOS transistor MN5 of pull-down side turns off. The potential of the output terminal BOUTP, i.e., the output signal OUT-MINUS attempts to rise from "L" (close to 0 V) toward "H" (VCC=3.3 V). At this time, the potential of the output terminal BOUTP rises, the capacitor element C1 is discharged. As a result, the fall rate of the potential of the node n1 becomes slower. Therefore, the fall rate at the time when the on-resistance of the NMOS transistor MN5 of pull-down side is increased by the potential fall of the node n1 is further made slow. Therefore, the rise rate of the potential of the output terminal BOUTP is also lowered. Therefore, the rise timing of the output signal OUT-PLUS becomes later than the timing of the change of the input signal IN from 5 V to 0 V. In FIG. 3, this delay time is denoted by t2.
In other words, when the potential (logic level) of the output node (drive signal source node) n1 of the voltage comparator circuit 21 changes with an amplitude between VDD and DGND, the rise rate and the fall rate of the potential of the node n1 is made slower by the function of the capacitor element C1, in the conventional output circuit shown in FIG. 2. And the time t1 elapsing until the NMOS transistor MN5 of pull-down side begins to turn on in the first output circuit differs from the time t2 elapsing until the NMOS transistor MN5 of pull-down side begins to turn off in the second output circuit (t1&gt;t2).
In specifications of USB, the rise time and the fall time of the output signals OUT-PLUS and OUT-MNUS and crosspoints where potentials of both signals cross each other are stipulated. In order to satisfy the specifications, there has been desired emergence of such an output circuit that the output signals OUT-PLUS and OUT-MNUS change nearly simultaneously in response to a change of the input signal IN.
In the convention output circuit, the PMOS transistor of pull-up side and the NMOS transistor of pull-down side are connected to the output terminal, and the feedback capacitor is connected to the output stage, as described above. When the potential of the drive signal source node connected to a first end side of the feedback capacitor changes, the rise rate and the fall rate of the potential of the node are made slower by the function of the capacitor element. In addition, since the time taken until the NMOS transistor of pull-down side begins to turn on differs from the time taken until the NMOS transistor of pull-down side begins to turn off, favorable input-output characteristics are not obtained. The convention output circuit has such problems.